Items where Author is "Pal, Ajit"

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Group by: Item Type | No Grouping
Number of items: 7.

Article

Mukherjee, Rajdeep ; Ghosh, Priyankar ; Dasgupta, Pallab ; Pal, Ajit (2013) An integrated approach for fine-grained power and temperature management during high-level synthesis Journal of Low Power Electronics, 9 (3). pp. 350-362. ISSN 1546-1998

Mukherjee, Rajdeep ; Ghosh, Priyankar ; Dasgupta, Pallab ; Pal, Ajit (2013) A multi-objective perspective for operator scheduling using finegrained DVS architectures International Journal of VLSI Design & Communication Systems, 4 (1). pp. 105-122. ISSN 0976-1527

Hazra, Aritra ; Goyal, Sahil ; Dasgupta, Pallab ; Pal, Ajit (2013) Formal verification of architectural power intent IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21 (1). pp. 78-91. ISSN 1063-8210

Hazra, Aritra ; Mukherjee, Rajdeep ; Dasgupta, Pallab ; Pal, Ajit ; Harer, Kevin M. ; Banerjee, Ansuman ; Mukherjee, Subhankar (2013) POWER-TRUCTOR: an integrated tool flow for formal verification and coverage of architectural power intent IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32 (11). pp. 1801-1813. ISSN 0278-0070

Conference or Workshop Item

Mukherjee, Rajdeep ; Dasgupta, Pallab ; Pal, Ajit ; Mukherjee, Subhankar (2013) Formal verification of hardware/software power management strategies In: 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 5-10 January 2013, Pune, India.

Mukherjee, Rajdeep ; Ghosh, Priyankar ; Dasgupta, Pallab ; Pal, Ajit (2013) Operator scheduling revisited: a multi-objective perspective for fine-grained DVS architecture In: Second International Conference on Advances in Computing and Information Technology (ACITY), 2012, July 13-15, 2012, Chennai, India.

Hazra, Aritra ; Mitra, Srobona ; Dasgupta, Pallab ; Pal, Ajit ; Bagchi, Debabrata ; Guha, Kaustav (2010) Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent In: 2010 47th ACM/IEEE Design Automation Conference (DAC), 13-18 June 2010, Anaheim, CA, USA.

This list was generated on Sun Oct 20 05:15:34 2024 UTC.