Sub-0.18 μm SOI MOSFETs using lateral asymmetric channel profile and Ge pre-amorphization salicide technology

Abstract

SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices. To reduce the source/drain parasitic resistance, a novel salicide technology with Ge pre-amorphization is used (Hsiao et al, IEEE SOI Conf., p. 126, 1996).