Cheng, Baohong ; Inani, A. ; Rao, R. ; Woo, J. C. S. (1999) Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS Technical Digest, 1999 Symposium on VLSI Technology, Kyoto, Japan . pp. 69-70.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/VLSIT.1999.799344
Abstract
The effects of channel engineering on device performance have been extensively investigated. The lateral asymmetric channel (LAC) MOSFETs show significantly higher Idsat and gmsat, lower Ioff, and superior short-channel performance compared with double-halo (DH) and conventional MOSFETs by effectively utilizing the velocity overshoot effects. It is demonstrated that the device switching speed of the LAC device at VDD=0.6 V is equivalent to that of a conventional device operated at VDD=1.5 V.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Technical Digest, 1999 Symposium on VLSI Technology, Kyoto, Japan. |
| ID Code: | 79801 |
| Deposited On: | 28 Jan 2012 11:43 |
| Last Modified: | 28 Jan 2012 11:43 |
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