Shrivastav, G. ; Mahapatra, S. ; Ramgopal Rao, V. ; Vasi, J. (2001) Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering Proceedings of the 14th International Conference on VLSI Design, Bangalore, India . pp. 475-478.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/ICVD.2001.902703
Abstract
A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D2FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Proceedings of the 14th International Conference on VLSI Design, Bangalore, India. |
| ID Code: | 79791 |
| Deposited On: | 28 Jan 2012 11:45 |
| Last Modified: | 28 Jan 2012 11:45 |
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