Effective dielectric thickness scaling for high-K gate dielectric MOSFETs

Abstract

It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO₂. In this work we have systematically evaluated the effective dielectric thickness for different K_gate to achieve targeted threshold voltage (V_t), drain-induced barrier lowering (DIBL) and I_on/I_off ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO₂ follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO₂ is replaced by a high-K dielectric.