Mohapatra, N. R. ; Nair, D. R. ; Mahapatra, S. ; Rao, V. R. ; Shukuri, S. (2003) The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs 33rd European Solid-State Device Research Conference (ESSDERC) 2003, Lisbon, Portugal . pp. 541-544.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/ESSDERC.2003.1256933
Abstract
The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to 33rd European Solid-State Device Research Conference (ESSDERC) 2003, Lisbon, Portugal. |
| ID Code: | 79769 |
| Deposited On: | 28 Jan 2012 11:49 |
| Last Modified: | 28 Jan 2012 11:49 |
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