Shrivastava, M. ; Verma, B. ; Baghini, M. S. ; Russ, C. ; Sharma, D. K. ; Gossner, H. ; Rao, V. R. (2009) Benchmarking the device performance at sub 22 nm node technologies using an SoC framework Proceedings of the International Electron Devices Meeting (IEDM) . pp. 1-4.
Full text not available from this repository.
Official URL: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arn...
Related URL: http://dx.doi.org/10.1109/IEDM.2009.5424311
Abstract
For the first time this paper makes an attempt at predicting the System-on-Chip (SoC) performance (i.e. logic, SRAM, ESD and I/O) of various sub 20 nm channel length planar and non-planar SOI devices using extensive & well calibrated 3D device and mixed-mode TCAD simulations. It has been shown that the non-planar devices such as FinFETs are not the ideal choice for SoC applications and perform poorly in comparison to the Ultra thin body (UTB) planar SOI MOSFETs. We further show different strategies to optimize the planar UTB MOSFETs for improved ESD robustness and I/O performance.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Proceedings of the International Electron Devices Meeting (IEDM). |
| ID Code: | 79733 |
| Deposited On: | 28 Jan 2012 11:57 |
| Last Modified: | 28 Jan 2012 11:57 |
Repository Staff Only: item control page
