Modelling and fault detection in microelectronic technologies

Abstract

The modelling and testing of microelectronic circuits for different technologies are presented. Rapid developments in these technologies have compelled the issue of reliability to become extremely important, A study of these developments, the commonly used microelectronic technologies, the causes of their failures and the circuit models are presented. The circuits are modelled at either the gate level or at the transistor level. Transistor-level modelling is given more emphasis because of some shortcomings in gate-level modelling. The transistor-level model assumes four logic values (0, 1, I, M), where I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non-classical transistor stuck faults can be analysed using the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for the specified subcircuit. To generate tests for single or multiple faults, a variant of the D-algorithm may be used.