An efficient scheme for interprocessor communication using dual-ported RAMs

Jagadish, N. ; Kumar, J. M. ; Patnaik, L. M. (1989) An efficient scheme for interprocessor communication using dual-ported RAMs Micro, IEEE, 9 (5). 10 - 19. ISSN 0272-1732

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Official URL: http://ieeexplore.ieee.org/search/freesrchabstract...

Related URL: http://dx.doi.org/10.1109/40.45822

Abstract

An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use intermediate buffers, input/output ports, or DMAs. The example of a three-dimensional cube is used to illustrate the advantages of this scheme. The implementation of the interprocessor communication scheme on a 64-node cube configuration is discussed.

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Deposited On:08 Sep 2011 13:12
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