Ravikanth, K. ; Sastry, P. S. ; Ramakrishnan, K. R. ; Venkatesh, Y. V. (1988) A reduction architecture for the optimal scheduling of binary trees Future Generation Computer Systems, 4 (3). pp. 225-233. ISSN 0167-739X
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Official URL: http://www.sciencedirect.com/science/article/pii/0...
Related URL: http://dx.doi.org/10.1016/0167-739X(88)90006-4
Abstract
This paper addresses the problem of designing a parallel reduction architecture for applicative languages. An interconnection network that allows for scheduling of binary trees of arbitrary depth is presented. It is shown that using a static scheduling strategy the architecture achieves optimal performance while scheduling complete binary trees. Some issues related to the design of a machine based on this network are also discussed.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Elsevier Science. |
| ID Code: | 57146 |
| Deposited On: | 26 Aug 2011 02:34 |
| Last Modified: | 26 Aug 2011 02:34 |
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