Validation and analysis of the future bus arbitration protocol: a case study

Boussinot, F ; Ramesh, S ; Shyamasundar, R. K. ; Simone, R. De. (1996) Validation and analysis of the future bus arbitration protocol: a case study Sadhana (Academy Proceedings in Engineering Sciences), 21 (2). pp. 185-211. ISSN 0256-2499

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Official URL: http://www.ias.ac.in/j_archive/sadhana/21/2/SA0210...

Related URL: http://dx.doi.org/10.1007/BF02745519

Abstract

In this paper, we use perfectly synchronous languages such as Esterel, for modelling Futurebus arbitration protocol. We show that the perfect synchrony aids in the formalization, testing, validating and verifying the protocol. We discuss solutions to the above protocol and show that properties such as mutual exclusion and deadlock-freedom can be established formally. Further, we show how the simulators can be used for testing and validation and can verify an instantiation of the protocol through algebraic tools such as auto/autograph.

Item Type:Article
Source:Copyright of this article belongs to Indian Academy of Sciences.
Keywords:Synchronous Languages; Futurebus Arbitration Protocol; Esterel
ID Code:56597
Deposited On:24 Aug 2011 10:58
Last Modified:24 Aug 2011 10:58

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