Anand, B. ; Desai, M. P. ; Rao, V. R. (2004) Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations IEEE Electron Device Letters, 25 (6). pp. 436-438. ISSN 0741-3106
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/LED.2004.829665
Abstract
The performance of partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) devices is degraded by the body capacitance and body resistance, which depend strongly on the silicon film thickness. We show that the body RC time constant reduces up to a certain value of silicon film thickness, and then saturates. However, delay of a DTMOS circuit is affected not only by the RC delay of the body but also by the additional load capacitance, which appears due to the gate to body contact. In this paper, we propose a model for PDSOI-DTMOS circuit delay, taking the effect of body parasitics into account, and use it to study the circuit delay as a function of silicon film thickness. Using this model, we show that the optimum value of silicon film thickness is approximately equal to the depletion width in the silicon film in a typical sub-100-nm PDSOI-DTMOS technology.
Item Type: | Article |
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Source: | Copyright of this article belongs to IEEE. |
ID Code: | 44457 |
Deposited On: | 22 Jun 2011 05:26 |
Last Modified: | 22 Jun 2011 05:26 |
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