A new method to characterize border traps in sub-micron transistors using hysteresis in the drain current

Abstract

In this paper, a new method for measuring border trap density (n_BT) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n_BT is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.