Kumar, D. V. ; Narasimhalu, K. ; Reddy, P. S. ; Shojaei-Baghini, M. ; Sharma, D. K. ; Patil, M. B. ; Rao, V. R. (2005) Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs IEEE Transactions on Electron Devices, 52 (7). pp. 1603-1609. ISSN 0018-9383
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/TED.2005.850941
Abstract
Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-μm technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device.
Item Type: | Article |
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Source: | Copyright of this article belongs to IEEE. |
ID Code: | 41555 |
Deposited On: | 30 May 2011 08:58 |
Last Modified: | 17 May 2016 23:14 |
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