Krishnamurthy, E. V. (1965) Algebra for (m,p) switching nets IEE Electronics Letters, 1 (3). pp. 58-59. ISSN 0013-5194
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Official URL: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arn...
Related URL: http://dx.doi.org/10.1049/el:19650056
Abstract
This paper describes the manner in which the (m, p) switching-network configurations combine. It is shown that this logic (algebra) is isomorphic to the many-valued logic of Post. Application of this logic in designing error-free logic systems is indicated.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institution of Engineering and Technology. |
| ID Code: | 28194 |
| Deposited On: | 14 Dec 2010 08:20 |
| Last Modified: | 04 Jun 2011 07:13 |
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