A laboratory model for system reliability analyzer

Abstract

A laboratory model of a reliability analyzer is described. The idea behind the development of such an analyzer is to provide an analogue model for determining all pathsets or cutsets of a system and thereby determining the system reliability when the system configuration is known along with the reliability of its constituent elements. Any system with unreliable branches and nodes can be simulated on the reliability analyzer using the logic gates. The analyzer provides tremendous flexibility in changing of the system configuration for reliability studies. The users require manually plugging in or out of a particular link to simulate addition or removal of a branch. The reliability parameters such as terminal reliability and global reliability in the case of a communication network can also be studied. Block diagram or fault tree approaches can be used to analyze a system on the analyzer described in this paper.