A Modified T-Structured Three-Level Inverter Configuration Optimized With Respect to PWM Strategy Used for Common-Mode Voltage Elimination

Abstract

This paper presents an optimized topology for a 3 - φ three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure 3 - φ inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI.