Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

Abstract

The origin of drain disturb in NOR Flash EEPROM cells under Channel Initiated Secondary Electron (CHISEL) programming operation is identified. A comparative study of drain disturb under Channel Hot Electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Full band Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.