Nair, D. R. ; Mohapatra, N. R. ; Mahapatra, S. ; Shukuri, S. ; Bude, J. D. (2004) Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation IEEE Transactions on Device and Materials Reliability, 4 (1). pp. 32-37. ISSN 1530-4388
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Official URL: http://ieeexplore.ieee.org/document/1284296/
Related URL: http://dx.doi.org/10.1109/TDMR.2004.824371
Abstract
Drain disturb is studied in NOR flash EEPROM cells under CHE and CHISEL programming operation, before and after repeated Program/Erase (P/E) cycling. Drain disturb is shown to originate from band-to-band tunneling under CHISEL operation, unlike under CHE operation where it originates from source-drain leakage. Under identical initial programming time, CHISEL operation always shows slightly lower Program/Disturb (P/D) margin before cycling but similar P/D margin after repetitive P/E cycling when compared to CHE operation. The degradation of gate coupling coefficient that affects source/drain leakage and the increase in trap-assisted band-to-band tunneling seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| ID Code: | 112664 |
| Deposited On: | 06 Apr 2018 05:37 |
| Last Modified: | 06 Apr 2018 05:37 |
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