Nair, D. R. ; Mahapatra, S. ; Shukuri, S. ; Bude, J. D. (2005) Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation IEEE Transactions on Electron Devices, 52 (4). pp. 534-540. ISSN 0018-9383
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Official URL: http://ieeexplore.ieee.org/document/1408155/
Related URL: http://dx.doi.org/10.1109/TED.2005.844741
Abstract
The impact of Program/Erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under Channel Hot Electron (CHE) and Channel-initiated Secondary Electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and full band Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | Hot Carriers; Band-to-band Tunneling (BTBT); Channel Hot Electron (CHE); Device Scaling; Drain Disturb; Channel-initiated Secondary Electron (CHISEL); Flash EEPROMs |
| ID Code: | 112663 |
| Deposited On: | 02 Apr 2018 09:38 |
| Last Modified: | 02 Apr 2018 09:38 |
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