Datta, A. ; Mahapatra, S. (2010) A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells Solid State Electronics, 54 (4). pp. 397-404. ISSN 0038-1101
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Official URL: https://www.sciencedirect.com/science/article/pii/...
Related URL: http://dx.doi.org/10.1016/j.sse.2009.11.006
Abstract
Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb and program speed. However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read VD. The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Elsevier Science. |
| Keywords: | Non-volatile Semiconductor Memory (NVSM); SONOS; 2-bit Operation; Halo Implant; Compensation Implant; Bit Coupling; Read Disturb; Program Speed; Cell Scaling |
| ID Code: | 112634 |
| Deposited On: | 02 Apr 2018 09:25 |
| Last Modified: | 02 Apr 2018 09:25 |
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