Paul, Abhijeet ; Sridhar, Ch. ; Gedam, Suny ; Mahapatra, S. (2006) Comprehensive simulation of program, erase and retention in charge trapping flash memories In: 2006 International Electron Devices Meeting, IEDM '06, 11-13 Dec, 2006, San Francisco, CA, USA.
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Official URL: http://ieeexplore.ieee.org/document/4154212/
Related URL: http://dx.doi.org/10.1109/IEDM.2006.346793
Abstract
A simulator is developed for SONOS flash memories to predict program (P), erase (E) and retention (R) behavior under uniform ID operation. It provides insight on the impact of trap parameters on P, E and R and can be used to optimize memory stacks.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| ID Code: | 112633 |
| Deposited On: | 12 Apr 2018 08:03 |
| Last Modified: | 12 Apr 2018 08:03 |
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