Mahapatra, S. ; Alam, M. A. ; Kumar, P. Bharath ; Dalei, T. R. ; Varghese, D. ; Saha, D. (2005) Negative Bias Temperature Instability in CMOS devices Microelectronic Engineering, 80 . pp. 114-121. ISSN 0167-9317
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Official URL: https://www.sciencedirect.com/science/article/pii/...
Related URL: http://dx.doi.org/10.1016/j.mee.2005.04.053
Abstract
This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence onstress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Elsevier Science. |
| Keywords: | MOSFET; NBTI; Interface Traps; Bulk Traps; Parameter Instability; Reaction-Diffusion Model; Hydrogen Diffusion |
| ID Code: | 112611 |
| Deposited On: | 02 Apr 2018 09:24 |
| Last Modified: | 02 Apr 2018 09:24 |
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