Goel, N. ; Mukhopadhyay, S. ; Nanaware, N. ; De, S. ; Pandey, R. K. ; Murali, K. V. R. M. ; Mahapatra, S. (2014) A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs In: 2014 IEEE International Conference on Reliability Physics Symposium, 1-5, June 2014, Waikoloa, HI, USA.
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Official URL: http://ieeexplore.ieee.org/document/6861100/
Related URL: http://dx.doi.org/10.1109/IRPS.2014.6861100
Abstract
DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2Å) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔVIT-IL) at Si/IL interface, hole trapping (ΔVHT) in IL bulk and trap generation (ΔVIT-HK) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict VT shift (ΔVT) during and after DC stress, dependence on Pulse Duty Cycle (PDC) and frequency (f) for AC stress and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied and end-of-life degradation has been estimated.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| ID Code: | 112581 |
| Deposited On: | 11 Apr 2018 11:20 |
| Last Modified: | 11 Apr 2018 11:20 |
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