Mukhopadhyay, S. ; Joshi, K. ; Chaudhary, V. ; Goel, N. ; De, S. ; Pandey, R. K. ; Murali, K. V. R. M. ; Mahapatra, S. (2014) Trap Generation in IL and HK layers during BTI/TDDB stress in scaled HKMG N and P MOSFETs In: 2014 IEEE International Conference on Reliability Physics Symposium, 1-5 June, 2014, Waikoloa, HI, USA.
Full text not available from this repository.
Official URL: http://ieeexplore.ieee.org/document/6861146/
Related URL: http://dx.doi.org/10.1109/IRPS.2014.6861146
Abstract
Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (VG,STR), time (tSTR) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to VT shift (ΔVT) is compared to ΔVT from ultra-fast measurements. A compact model is used to predict overall BTI ΔVT considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | DFT Simulation; Trap Generation; Trapping; DCIV; SILC; NBTI; PBTI; UFM-MSM; IL Scaling; Ov Defects |
| ID Code: | 112580 |
| Deposited On: | 11 Apr 2018 11:14 |
| Last Modified: | 11 Apr 2018 11:14 |
Repository Staff Only: item control page
