DC/AC BTI variability of SRAM circuits simulated using a physics-based compact model

Abstract

A physics-based compact model has been developed to predict DC and AC Bias Temperature Instability (BTI) induced threshold voltage shift (ΔVT) in HKMG MOSFETs. For Negative BTI (NBTI) in p-MOSFETs, the model uses Si/IL interface trap generation (ΔV_IT-IL) and hole trapping in IL bulk (ΔV_IT-IL). For Positive BTI (PBTI) in n-MOSFETs, it uses IL/HK interface trap generation (ΔV_IT-HK) and electron trapping in HK bulk (ΔV_ET-HK). The model framework has been extended to generate device level stochastic ΔV_T distributions and eventually V_T distributions by taking time zero variability into account. V_T distributions with stress time for DC and AC stress and for different duty cycles for AC stress are investigated. The resulting impact on 6T and 8T SRAM cells is studied for read as well as first and second write operations after different stress time and activity conditions and long time failure probabilities are obtained.