Impact of BTI on dynamic and static power: From the physical to circuit level

Abstract

We investigate in this work, for the first time, the impact that BTI has on dynamic and static power from the physical level all the way up to the circuit level. Unlike the impact of BTI on delay, which has been largely explored during the last decade, only a few works recently aimed to study the impact of BTI on circuits' power. Our investigation revealed that because state of the art considers solely the effect of BTI on the threshold voltage of transistors, it significantly (> 50%) overestimates the beneficial impact of BTI on power. We demonstrate how, in fact, beside threshold voltage, the impact of BTI on other crucial MOSFET parameters like carriers mobility, sub-threshold slope and gate-drain capacitance together with the existing interdependencies between them must additionally be considered for correct power modeling. We also demonstrate that the impact of BTI on the dynamic and static power is non-uniform across standard cells. Therefore, studying the impact of BTI on solely one or a couple of cells, as state of the art does, is very insufficient. Hence, to accurately capture the impact of BTI on the total power of a circuit, the standard cell library needs to be fully re-characterized in the scope of all BTI-induced degradations and then be employed within existing EDA tool flows towards performing an aging-aware power analysis. Achieving this goal concisely represents the core of this paper.