Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Abstract

Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN_IT) and trapping of holes in gate insulator traps (ΔN_HT). However, the isolation methods and the relative dominance of ΔN_IT and ΔN_HT, time constants of ΔN_IT and ΔN_HT for stress, recovery and associated temperature (T) activation and whether ΔN_IT recovers or remains permanent after stress, are widely debated. The resolution of such disputes is necessary to develop a reliable NBTI model. This work uses carefully designed measurements and simulations to resolve the aforementioned disputes. The contribution of ΔN_IT and ΔN_HT on overall threshold voltage shift (ΔV_T) is determined. Kinetics of ΔN_IT and ΔN_HT during stress and recovery, T activation and associated time constants are verified in both large and small area devices. Existing theoretical models for ΔN_IT and ΔN_HT are benchmarked and validated against DC and AC experiments. Capability of the existing models for predicting end-of-life ΔV_T is demonstrated.