Joshi, K. ; Hung, S. ; Mukhopadhyay, S. ; Sato, T. ; Bevan, M. ; Rajamohanan, B. ; Wei, A. ; Noori, A. ; McDougall, B. ; Ni, C. ; Lazik, C. ; Saheli, G. ; Liu, P. ; Chu, D. ; Date, L. ; Datta, S. ; Brand, A. ; Swenberg, J. ; Mahapatra, S. (2013) Scaled gate stacks for sub-20-nm CMOS logic applications through integration of thermal IL and ALD HfOx IEEE Electron Device Letters, 34 (1). pp. 3-5. ISSN 0741-3106
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Official URL: http://ieeexplore.ieee.org/document/6340307/author...
Related URL: http://dx.doi.org/10.1109/LED.2012.2222338
Abstract
The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on Negative-bias Temperature Instability and Positive-bias Temperature Instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to ∼6Å, with excellent gate leakage, mobility and world-class BTI. The mechanism responsible for improved BTI is discussed.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | Positive-bias Temperature Instability (PBTI); DCIV; Equivalent Oxide Thickness (EOT) Scaling; Flicker Noise; Gate Leakage; HKMG; Interlayer (IL) Scaling; Mobility; Negative-bias Temperature Instability (NBTI) |
| ID Code: | 112491 |
| Deposited On: | 02 Apr 2018 06:50 |
| Last Modified: | 02 Apr 2018 06:50 |
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