On the impact of time-zero variability, variable NBTI and stochastic TDDB on SRAM cells

Abstract

We propose a Monte Carlo (MC) simulation framework for circuits taking into account the Time-dependent Dielectric Breakdown (TDDB) statistics along with time-0 variability and variable Negative-Bias Temperature Instability (NBTI) under circuit operating conditions in SPICE environment. MC simulation is performed with the proposed framework for ∼100 k Static Random Access Memory (SRAM) cells using experimentally calibrated device-level degradation distribution. Cell performance degradation is compared for both planar and FinFET-based SRAM cells. It is shown that TDDB can significantly impact the SRAM failure probability even under usual circuit operation. It is reported that FinFET-based cells show far more robustness toward cell performance degradation than their planar counterparts.