Mukhopadhyay, Subhadeep ; Parihar, Narendra ; Goel, Nilesh ; Mahapatra, Souvik (2017) A comprehensive DC and AC PBTI modeling framework for HKMG n-MOSFETs IEEE Transactions on Electron Devices, 64 (4). pp. 1474-1481. ISSN 0018-9383
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Official URL: http://ieeexplore.ieee.org/document/7867042/
Related URL: http://dx.doi.org/10.1109/TED.2017.2670260
Abstract
A physics-based modeling framework is proposed to calculate the threshold voltage shift (ΔVT) in planar High-k Metal Gate (HKMG) n-MOSFETs for positive bias temperature instability (PBTI). Overall ΔVT is estimated using the uncorrelated contributions from the Trap Generation (TG) and the electron trapping subcomponents. The time evolution of ΔVT, measured using an ultrafast measure-stress-measure method during DC and AC stress and after Dc stress, is predicted for different experimental conditions. The modeled TG component is verified by independent direct-current I-V method. The proposed model explains PBTI in differently processed HKMG gate stacks.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | AC Stress; DC Stress; Electron Trapping (TP); High-k Metal Gate (HKMG); Positive Bias Temperature Instability (PBTI); Trap Generation (TG); Ultrafast Measure-stress-measure (UF-MSM) |
| ID Code: | 112477 |
| Deposited On: | 02 Apr 2018 06:03 |
| Last Modified: | 02 Apr 2018 06:03 |
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