Dobriyal, Arun ; Gonnabattula, Rahul ; Dasgupta, Pallab ; Mandal, Chittaranjan R. (2012) Workload driven power domain partitioning In: 16th International VLSI Design and Test Symposium, VDAT 2012, July 1-4, 2012, Shibpur, India.
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Official URL: http://link.springer.com/chapter/10.1007%2F978-3-6...
Related URL: http://dx.doi.org/10.1007/978-3-642-31494-0_17
Abstract
This paper presents a formulation for the problem of partitioning the set of components on a power rail of a low power integrated circuit into power domains based on the usage patterns given by an application specific workload. We present an analysis of the underlying problem, proving that the problem is NP-complete. We propose a greedy algorithm for this problem and compare its solutions with a more exhaustive search based on a genetic algorithm formulation. It is shown through empirical evaluation that the greedy algorithm is in general a well suited algorithm for this problem.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Springer-Verlag Berlin Heidelberg. |
| Keywords: | Low Power Circuits; Partitioning; CAD |
| ID Code: | 102316 |
| Deposited On: | 09 Mar 2018 10:13 |
| Last Modified: | 09 Mar 2018 10:13 |
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