Banerjee, Ansuman ; Pal, Bhaskar ; Das, Sayantan ; Kumar, Abhijeet ; Dasgupta, Pallab (2006) Test generation games from formal specifications In: 2006 43rd ACM/IEEE Design Automation Conference, 24-28 July 2006, San Francisco, CA.
Full text not available from this repository.
Official URL: http://ieeexplore.ieee.org/document/1688911/
Related URL: http://dx.doi.org/10.1145/1146909.1147120
Abstract
In this paper, we present methods for automatic test generation from formal specifications. These are used to create intelligent test benches that are able to cover corner case behaviors in much less time. We have developed a prototype tool for intelligent test generation within the layered test bench architecture proposed in RVM. We present results on verification IPs of standard bus protocols to show the effectiveness of our approach.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | Realizability; Verification; Test Generation; Vacuity |
| ID Code: | 101685 |
| Deposited On: | 09 Mar 2018 10:17 |
| Last Modified: | 09 Mar 2018 10:17 |
Repository Staff Only: item control page
