Mitra, Srobona ; Ghosh, Priyankar ; Dasgupta, Pallab ; Chakrabarti, Partha P. (2009) Incremental verification techniques for an updated architectural specification In: 2009 Annual IEEE India Conference, 18-20 December 2009, Gandhinagar, Gujarat, India.
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Official URL: http://ieeexplore.ieee.org/document/5409403/
Related URL: http://dx.doi.org/10.1109/INDCON.2009.5409403
Abstract
This paper explores the utility of making use of previously proved component properties and available simulation traces at the component and system level of a composite design for proving a newly added architectural property of the design. We present two techniques of reusing these prior verification results for proving or disproving the architectural property without doing full-scale formal verification of it on the total design from scratch, which runs into capacity issues, or running the already run simulations once again with this new property as an assertion, which is extremely time-consuming and leads to significant wastage of validation effort. We have experimented with our proposed approach on AMBA AHB example and have obtained encouraging results.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronics Engineers. |
| Keywords: | AMBA AHB; Incremental Verification Technique; Architectural Specification; Formal Verification |
| ID Code: | 101668 |
| Deposited On: | 12 Dec 2016 09:59 |
| Last Modified: | 12 Dec 2016 09:59 |
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