Backward reasoning with formal properties: a methodology for bug isolation on simulation traces

Komuravelli, Anvesh ; Mitra, Srobona ; Banerjee, Ansuman ; Dasgupta, Pallab (2011) Backward reasoning with formal properties: a methodology for bug isolation on simulation traces In: 2011 Asian Test Symposium, 20-23 November 2011, New Delhi, India.

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Official URL: http://ieeexplore.ieee.org/document/6114496/

Related URL: http://dx.doi.org/10.1109/ATS.2011.54

Abstract

Automated methods for bug localization for hardware designs typically work on the design implementation to root-cause a given bug. This paper presents a novel debugging approach where instead of using the design implementation in the debugging process, we use causal deduction using formal properties scattered across the design to locate the bug. This has two advantages, namely, (a) the reasoning takes place in the property space instead of the state space of the implementation, which enhances scalability, and (b) new properties can be added in hindsight to perform what-if analysis, which is less expensive than modifying the implementation for each alternative. Experimental results demonstrate the scalability of the approach in debugging designs with large property suites.

Item Type:Conference or Workshop Item (Paper)
Source:Copyright of this article belongs to Institute of Electrical and Electronics Engineers.
Keywords:Debugging; Cognition; Cost Accounting; Scalability; Algorithm Design And Analysis; Computer Bugs; Protocols
ID Code:101632
Deposited On:12 Dec 2016 10:16
Last Modified:12 Dec 2016 10:16

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