BUSpec: a framework for generation of verification aids for standard bus protocol specifications

Abstract

A typical verification intellectual property (VIP) of a bus protocol such as ARM advanced micro-controller bus architecture (AMBA) or PCI consists of a set of assertions and associated verification aids such as test-benches, design-ware models and coverage metrics. While several languages have been formalized for specifying assertions (examples include Open-Vera Assertions, Sugar, ForSpec, System Verilog Assertions, etc.), it is widely accepted that the tasks of writing protocol-compliant models and test-benches that produce protocol compliant stimuli are also tasks of equal importance. In this paper, we present a platform for high-level specification of a bus protocol in a hierarchical manner and an automated methodology for generating a variety of verification aids that supplement the set of assertions in a VIP. We also show that the verification aids can be efficiently used to determine the completeness of the set of assertions in a simulation-based verification environment.