Pal, Bhaskar ; Banerjee, Ansuman ; Sinha, Arnab ; Dasgupta, Pallab (2008) Accelerating assertion coverage with adaptive testbenches IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27 (5). pp. 967-972. ISSN 0278-0070
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Official URL: http://ieeexplore.ieee.org/document/4492842/
Related URL: http://dx.doi.org/10.1109/TCAD.2008.917975
Abstract
We present a new approach to bias random test generation for accelerating assertion coverage. The novelty of the proposed approach is that it treats the design under test as a black box and attempts to steer the simulation toward coverage points that are relevant for targeted assertions purely through external control. We present this approach over three different models with varying degrees of observability and control. The results demonstrate a significant speedup in assertion coverage as compared to randomized simulation.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | Test Generation; Design Verification; Functional Coverage |
| ID Code: | 101410 |
| Deposited On: | 09 Mar 2018 10:17 |
| Last Modified: | 09 Mar 2018 10:17 |
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