Roy, S. ; Chakrabarti, P. P. ; Dasgupta, P. (2008) Satisfiability models for maximum transition power IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16 (8). pp. 941-951. ISSN 1063-8210
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Official URL: http://ieeexplore.ieee.org/document/4555250/
Related URL: http://dx.doi.org/10.1109/TVLSI.2008.2000322
Abstract
A satisfiability-based technique for symbolic modeling of event propagation in a circuit is presented in this paper which captures the events in the internal nodes of the circuit with a high level of detail. The model is used to accurately measure the peak single cycle transition power consumption in combinational and sequential circuits, which is closely affected by the switching activity in the circuit. Our technique is scalable, and adapts easily to ever increasing sizes of the custom cells (building blocks) in today's industry, without compromising on accuracy and correctness.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | SAT; Event Modeling; Peak Transition Power |
| ID Code: | 101408 |
| Deposited On: | 09 Mar 2018 10:17 |
| Last Modified: | 09 Mar 2018 10:17 |
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