Bounded delay timing analysis and power estimation using SAT

Abstract

This paper presents a satisfiability based approach that can be used for accurate estimation of both the critical delay and dynamic transition power consumption of circuits using an event propagation model. The accuracy of the model depends on the accuracy of the gate delays. The speed and efficiency of modern Boolean SAT solvers permits us to model complicated delay models like the Bounded Delay Model, which is better able to capture realistic variations in gate delays due to process variations and changes in operating conditions. We show that timing analysis with bounded delays yields a more accurate critical delay for a circuit than with fixed gate delays. In spite of the high complexity due to unpredictable gate delays, our SAT based approach gives good performance on benchmark circuits, even with a Bounded Delay Model derived from a real industrial library.