Das, Sourasis ; Banerjee, Ansuman ; Dasgupta, Pallab (2012) Early analysis of critical faults: an approach to test generation from formal specifications IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31 (3). pp. 447-451. ISSN 0278-0070
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Official URL: http://ieeexplore.ieee.org/document/6152773/
Related URL: http://dx.doi.org/10.1109/TCAD.2011.2171183
Abstract
This paper presents a formal methodology for test generation from formal specifications. Our method can be used for test generation for critical faults in component-based designs. Test generation for critical faults is done entirely using formal specifications and therefore the theory inherently guarantees that a generated test will be applicable to any implementation of the specifications. The theory makes fault analysis possible at an abstract level of design where the complete logic is not specified.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | Circuit Faults; Cost Accounting; Integrated Circuit Modeling; Computational Modeling; Safety; Fault Tolerance; Fault Tolerant Systems |
| ID Code: | 101373 |
| Deposited On: | 12 Dec 2016 11:51 |
| Last Modified: | 12 Dec 2016 11:51 |
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