Mukherjee, Subhankar ; Dasgupta, Pallab (2012) Computing minimal debugging windows in failure traces of AMS assertions IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31 (11). pp. 1776-1781. ISSN 0278-0070
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Official URL: http://ieeexplore.ieee.org/document/6331651/
Related URL: http://dx.doi.org/10.1109/TCAD.2012.2203599
Abstract
There has been considerable focus recently on research on developing assertion checking capability with analog and mixed-signal (AMS) simulators. Such tools must be able to detect failures of assertions in simulation traces and report the windows in which failures have been detected. Due to the dense real time semantics of AMS assertions, the task of identifying the minimal debugging window for each failure is not a trivial problem. This paper addresses the problem of computing the minimal debugging window in failure traces for AMS assertions and presents an algorithm which is linear in regards to the size of the assertion and the size of the trace.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Institute of Electrical and Electronic Engineers. |
| Keywords: | Temporal Logic; Counterexample; Failure Trace |
| ID Code: | 101118 |
| Deposited On: | 12 Dec 2016 12:01 |
| Last Modified: | 12 Dec 2016 12:01 |
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