The spring scheduling co-processor: a scheduling accelerator

Burleson, W. ; Ko, J. ; Niehaus, D. ; Ramamritham, K. ; Stankovic, J. A. ; Wallace, G. ; Weems, C. (1993) The spring scheduling co-processor: a scheduling accelerator Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors . pp. 140-144.

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We present a novel co-processor for multiprocessor scheduling in the Spring real-time operating system. Since most dynamic scheduling problems are NP-complete, we use a heuristic algorithm which uses a smart searching scheme to find a feasible schedule for a set of specified tasks and hard deadlines. A parallel VLSI architecture for scheduling is developed that can be scaled for different numbers of tasks, numbers of resources, internal wordlengths, and future IC technologies. The scheduling architecture is implemented in a 0.8μ CMOS technology and uses an advanced clocking scheme to allow further scaling to future technologies. With an internal clock rate of 100 MHz, a speed increase of two orders of magnitude is expected for scheduling tasks, thus removing a major bottleneck in real-time systems.

Item Type:Article
Source:Copyright of this article belongs to IEEE Press.
ID Code:94318
Deposited On:23 Aug 2012 11:11
Last Modified:23 Aug 2012 11:11

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