Mahapatra, S. ; Ramgopal Rao, V. ; Manjula Rani, K. N. ; Parikh, C. D. ; Vasi, J. ; Cheng, B. ; Khare, M. ; Woo, J. C. S. (1999) 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric Technical Digest, 1999 Symposium on VLSI Technology, Kyoto, Japan . pp. 79-80.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/VLSIT.1999.799349
Abstract
Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO2 MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Technical Digest, 1999 Symposium on VLSI Technology, Kyoto, Japan. |
| ID Code: | 79800 |
| Deposited On: | 28 Jan 2012 11:43 |
| Last Modified: | 28 Jan 2012 11:43 |
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