Dixit, A. ; Pal, D. K. ; Roy, J. N. ; Ramgopal Rao, V. (2002) Channel engineering for sub-micron CMOS technologies Proceedings of the 11th International Workshop on The Physics of Semiconductor Devices, Delhi, India, 4746 (2). pp. 637-640.
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Abstract
In this work, we have applied channel-engineering strategies for the Semiconductor Complex Limited (SCL) 0.8 µm CMOS process and studied the performance advantages using extensive 2-D device simulations. Our results clearly indicate that, with minimum adjustments to the process flow, one can achieve improved performance by appropriate choice of channel engineering techniques.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Proceedings of the 11th International Workshop on The Physics of Semiconductor Devices, Delhi, India. |
| ID Code: | 79784 |
| Deposited On: | 28 Jan 2012 11:46 |
| Last Modified: | 28 Jan 2012 11:46 |
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