Parasitic effects depending on shape of spacer region on FinFETs

Abstract

Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the spacer region. The gate delay characteristic of the FinFETs was optimized by gradual expansion with triangular shape. It was indicated that not only parasitic resistance but also parasitic capacitance on the spacer region was significant for transistor performance.