Sachid, A. B. ; Kulkarni, G. S. ; Baghini, M. S. ; Sharma, D. K. ; Rao, V. R. (2009) Highly robust nanoscale planar double-gate MOSFET device and SRAM cell immune to gate-misalignment and process variations Proceedings of the IEEE International Workshop on Electron Devices & Semiconductor Technology, Mumbai, India . pp. 1-4.
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Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb...
Related URL: http://dx.doi.org/10.1109/EDST.2009.5166136
Abstract
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices. For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET. Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved. A standard 6T-SRAM cell designed using the optimized devices shows better read and hold static noise margins, and lower variations in SNM and leakage power compared to a conventional DG-MOSFET.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Proceedings of the IEEE International Workshop on Electron Devices & Semiconductor Technology, Mumbai, India. |
| ID Code: | 79739 |
| Deposited On: | 28 Jan 2012 11:56 |
| Last Modified: | 28 Jan 2012 11:56 |
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