Ray, Prasenjit ; Seena, V. ; Apte, Prakash R. ; Rao, Ramgopal (2011) High yield polymer MEMS process for CMOS/MEMS integration MRS proceedings, 1299 . pp. 1-5. ISSN 1946-4274
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Official URL: http://journals.cambridge.org/abstract_S1946427411...
Related URL: http://dx.doi.org/10.1557/opl.2011.58
Abstract
MEMS community is increasingly using SU-8 as a structural material because it is self-patternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper.
| Item Type: | Article |
|---|---|
| Source: | Copyright of this article belongs to Cambridge University Press. |
| Keywords: | Polymer; Structural; Composite |
| ID Code: | 79717 |
| Deposited On: | 28 Jan 2012 12:04 |
| Last Modified: | 28 Jan 2012 12:04 |
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