A systolic algorithm for hidden surface removal

Das, S. R. ; Vaidya, N. H. ; Patnaik, L. M. ; Mathias, P. C. (1990) A systolic algorithm for hidden surface removal Parallel Computing, 15 (1-3). pp. 277-289. ISSN 0167-8191

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Official URL: http://www.sciencedirect.com/science/article/pii/0...

Related URL: http://dx.doi.org/10.1016/0167-8191(90)90050-J


With the advent of VLSI it has become possible to map parallel algorithms for compute-bound problems directly on silicon. Systolic architecture is very good candidate for VLSI implementation because of its regular and simple design, and regular communication pattern. In this paper, a systolic algorithm and corresponding systolic architecture, a linear systolic array, for the scanline-based hidden surface removal problem in three-dimensional computer graphics have been proposed. The algorithm is based on the concept of sample spans or intervals. The worst case time taken by the algorithm is O(n), n being the number of segments in a scanline. The time taken by the algorithm for a given scene depends on the scene itself, and on an average considerable improvement over the worst case behaviour is expected. A pipeline scheme for handling the I/O process has also been proposed which is suitable for VLSI implementation of the algorithm.

Item Type:Article
Source:Copyright of this article belongs to Elsevier Science.
Keywords:VLSI Implementation; Systolic Algorithm; Hidden Surface Removal Problem; Systolic Architecture; Simulation Results
ID Code:70159
Deposited On:18 Nov 2011 12:10
Last Modified:18 Nov 2011 12:10

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