A systolic evaluator for linear, quadratic, and cubic expressions

Mathias, P. C. ; Patnaik, L. M. (1988) A systolic evaluator for linear, quadratic, and cubic expressions Journal of Parallel and Distributed Computing, 5 (6). pp. 729-740. ISSN 0743-7315

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Official URL: http://www.sciencedirect.com/science/article/pii/0...

Related URL: http://dx.doi.org/10.1016/0743-7315(88)90039-1


High-speed evaluation of a large number of linear, quadratic, and cubic expressions is very important for the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have actually been built by H. Fuchs and his group to evaluate linear expressions. In this paper, we describe a topological variant of Fuchs' pixel planes which can evaluate linear, quadratic, cubic, and higher-order polynomials. In our design, we make use of local interconnections only, i.e., interconnections between neighboring processing cells. This leads to the concept of tiling the processing cells for VLSI implementation.

Item Type:Article
Source:Copyright of this article belongs to Elsevier Science.
ID Code:70158
Deposited On:18 Nov 2011 12:10
Last Modified:18 Nov 2011 12:10

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