Worst-case design of dc transistor circuits

Abstract

The worst-case design of nonlinear dc transistor circuits is treated as a constrained minimax problem. The nonlinear network equations are treated as equality constraints on the design parameters. A recently proposed algorithm for constrained minimax optimization is then applied to solve the problem. A numerical example is taken to show that for worst-case design it is more natural to optimize a minimax performance function than a least-squares one.